diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 58d77dc..774a7d5 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -6,5 +6,6 @@
 #
 
 obj-y += board.o
+obj-y += ddr3_cfg.o
 obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
 obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
new file mode 100644
index 0000000..6e55af9
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -0,0 +1,130 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <i2c.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR3 PHY configuration data with 1600M rate, 8GB size */
+struct ddr3_phy_config ddr3phy_1600_8g = {
+	.pllcr          = 0x0001C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0D861A80ul,
+	.ptr4           = 0x0C827100ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0xA19DBB66ul,
+	.dtpr1          = 0x32868300ul,
+	.dtpr2          = 0x50035200ul,
+	.mr0            = 0x00001C70ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000018ul,
+	.dtcr           = 0x730035C7ul,
+	.pgcr2          = 0x00F07A12ul,
+	.zq0cr1         = 0x0000005Dul,
+	.zq1cr1         = 0x0000005Bul,
+	.zq2cr1         = 0x0000005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
+struct ddr3_emif_config ddr3_1600_8g = {
+	.sdcfg          = 0x6200CE6Aul,
+	.sdtim1         = 0x16709C55ul,
+	.sdtim2         = 0x00001D4Aul,
+	.sdtim3         = 0x435DFF54ul,
+	.sdtim4         = 0x553F0CFFul,
+	.zqcfg          = 0xF0073200ul,
+	.sdrfc          = 0x00001869ul,
+};
+
+#ifdef CONFIG_K2HK_EVM
+/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
+struct ddr3_phy_config ddr3phy_1333_2g = {
+	.pllcr          = 0x0005C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0B4515C2ul,
+	.ptr4           = 0x0A6E08B4ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x8558AA55ul,
+	.dtpr1          = 0x32857280ul,
+	.dtpr2          = 0x5002C200ul,
+	.mr0            = 0x00001A60ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000010ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F065B8ul,
+	.zq0cr1         = 0x0000005Dul,
+	.zq1cr1         = 0x0000005Bul,
+	.zq2cr1         = 0x0000005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
+struct ddr3_emif_config ddr3_1333_2g = {
+	.sdcfg          = 0x62008C62ul,
+	.sdtim1         = 0x125C8044ul,
+	.sdtim2         = 0x00001D29ul,
+	.sdtim3         = 0x32CDFF43ul,
+	.sdtim4         = 0x543F0ADFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001457ul,
+};
+#endif
+
+int ddr3_get_dimm_params(char *dimm_name)
+{
+	int ret;
+	int old_bus;
+	u8 spd_params[256];
+
+	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+	old_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+	i2c_set_bus_num(old_bus);
+
+	dimm_name[0] = '\0';
+
+	if (ret) {
+		puts("Cannot read DIMM params\n");
+		return 1;
+	}
+
+	/*
+	 * We need to convert spd data to dimm parameters
+	 * and to DDR3 EMIF and PHY regirsters values.
+	 * For now we just return DIMM type string value.
+	 * Caller may use this value to choose appropriate
+	 * a pre-set DDR3 configuration
+	 */
+
+	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+	dimm_name[18] = '\0';
+
+	return 0;
+}
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
new file mode 100644
index 0000000..d14bac3
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -0,0 +1,21 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR3_CFG_H
+#define __DDR3_CFG_H
+
+extern struct ddr3_phy_config ddr3phy_1600_8g;
+extern struct ddr3_emif_config ddr3_1600_8g;
+
+extern struct ddr3_phy_config ddr3phy_1333_2g;
+extern struct ddr3_emif_config ddr3_1333_2g;
+
+int ddr3_get_dimm_params(char *dimm_name);
+
+#endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index 31e9c31..21a5a0a 100644
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -8,287 +8,18 @@
  */
 
 #include <common.h>
+#include "ddr3_cfg.h"
 #include <asm/arch/ddr3.h>
 #include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1600_64A = {
-	.pllcr		= 0x0001C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0D861A80ul,
-	.ptr4		= 0x0C827100ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0xA19DBB66ul,
-	.dtpr1		= 0x12868300ul,
-	.dtpr2		= 0x50035200ul,
-	.mr0		= 0x00001C70ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000018ul,
-	.dtcr		= 0x730035C7ul,
-	.pgcr2		= 0x00F07A12ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_64 = {
-	.sdcfg		= 0x6200CE6aul,
-	.sdtim1		= 0x16709C55ul,
-	.sdtim2		= 0x00001D4Aul,
-	.sdtim3		= 0x435DFF54ul,
-	.sdtim4		= 0x553F0CFFul,
-	.zqcfg		= 0xF0073200ul,
-	.sdrfc		= 0x00001869ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1600_32 = {
-	.pllcr		= 0x0001C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0D861A80ul,
-	.ptr4		= 0x0C827100ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0xA19DBB66ul,
-	.dtpr1		= 0x12868300ul,
-	.dtpr2		= 0x50035200ul,
-	.mr0		= 0x00001C70ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000018ul,
-	.dtcr		= 0x730035C7ul,
-	.pgcr2		= 0x00F07A12ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_32 = {
-	.sdcfg		= 0x6200DE6aul,
-	.sdtim1		= 0x16709C55ul,
-	.sdtim2		= 0x00001D4Aul,
-	.sdtim3		= 0x435DFF54ul,
-	.sdtim4		= 0x553F0CFFul,
-	.zqcfg		= 0x70073200ul,
-	.sdrfc		= 0x00001869ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64A = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
-			   NOSRA_MASK | UDIMM_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27) | (1 << 29)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_64 = {
-	.sdcfg		= 0x62008C62ul,
-	.sdtim1		= 0x125C8044ul,
-	.sdtim2		= 0x00001D29ul,
-	.sdtim3		= 0x32CDFF43ul,
-	.sdtim4		= 0x543F0ADFul,
-	.zqcfg		= 0xF0073200ul,
-	.sdrfc		= 0x00001457ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1333_32 = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
-			   NOSRA_MASK | UDIMM_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27) | (1 << 29)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_32 = {
-	.sdcfg		= 0x62009C62ul,
-	.sdtim1		= 0x125C8044ul,
-	.sdtim2		= 0x00001D29ul,
-	.sdtim3		= 0x32CDFF43ul,
-	.sdtim4		= 0x543F0ADFul,
-	.zqcfg		= 0xf0073200ul,
-	.sdrfc		= 0x00001457ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64 = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-/******************************************************/
-
-/* DDR PHY Configs Updated for PG 2.0
- * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */
-static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = {
-	.pllcr          = 0x0001C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x0D861A80ul,
-	.ptr4           = 0x0C827100ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0xA19DBB66ul,
-	.dtpr1          = 0x32868300ul,
-	.dtpr2          = 0x50035200ul,
-	.mr0            = 0x00001C70ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000018ul,
-	.dtcr           = 0x730035C7ul,
-	.pgcr2          = 0x00F07A12ul,
-	.zq0cr1         = 0x0001005Dul,
-	.zq1cr1         = 0x0001005Bul,
-	.zq2cr1         = 0x0001005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = {
-	.pllcr          = 0x0005C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x0B4515C2ul,
-	.ptr4           = 0x0A6E08B4ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0x8558AA55ul,
-	.dtpr1          = 0x32857280ul,
-	.dtpr2          = 0x5002C200ul,
-	.mr0            = 0x00001A60ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000010ul,
-	.dtcr           = 0x710035C7ul,
-	.pgcr2          = 0x00F065B8ul,
-	.zq0cr1         = 0x0001005Dul,
-	.zq1cr1         = 0x0001005Bul,
-	.zq2cr1         = 0x0001005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-int get_dimm_params(char *dimm_name)
-{
-	u8 spd_params[256];
-	int ret;
-	int old_bus;
-
-	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
-	old_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
-	i2c_set_bus_num(old_bus);
-
-	dimm_name[0] = '\0';
-
-	if (ret) {
-		puts("Cannot read DIMM params\n");
-		return 1;
-	}
-
-	/*
-	 * We need to convert spd data to dimm parameters
-	 * and to DDR3 EMIF and PHY regirsters values.
-	 * For now we just return DIMM type string value.
-	 * Caller may use this value to choose appropriate
-	 * a pre-set DDR3 configuration
-	 */
-
-	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
-	dimm_name[18] = '\0';
-
-	return 0;
-}
 
 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
-struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
-struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
 
 void ddr3_init(void)
 {
 	char dimm_name[32];
 
-	get_dimm_params(dimm_name);
+	ddr3_get_dimm_params(dimm_name);
 
 	printf("Detected SO-DIMM [%s]\n", dimm_name);
 
@@ -299,21 +30,25 @@
 				/* PG 2.0 */
 				/* Reset DDR3A PHY after PLL enabled */
 				ddr3_reset_ddrphy();
+				ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+				ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+				ddr3phy_1600_8g.zq2cr1 |= 0x10000;
 				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1600_64A_pg2);
+						 &ddr3phy_1600_8g);
 			} else {
 				/* PG 1.1 */
 				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1600_64A);
+						 &ddr3phy_1600_8g);
 			}
 
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1600_64);
+					  &ddr3_1600_8g);
 			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
 		} else {
-			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32);
+			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+			ddr3_1600_8g.sdcfg |= 0x1000;
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1600_32);
+					  &ddr3_1600_8g);
 			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
 		}
 	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
@@ -323,27 +58,27 @@
 				/* PG 2.0 */
 				/* Reset DDR3A PHY after PLL enabled */
 				ddr3_reset_ddrphy();
+				ddr3phy_1333_2g.zq0cr1 |= 0x10000;
+				ddr3phy_1333_2g.zq1cr1 |= 0x10000;
+				ddr3phy_1333_2g.zq2cr1 |= 0x10000;
 				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1333_64A_pg2);
+						 &ddr3phy_1333_2g);
 			} else {
 				/* PG 1.1 */
 				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1333_64A);
+						 &ddr3phy_1333_2g);
 			}
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1333_64);
+					  &ddr3_1333_2g);
 		} else {
-			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32);
+			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
+			ddr3_1333_2g.sdcfg |= 0x1000;
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1333_32);
+					  &ddr3_1333_2g);
 		}
 	} else {
 		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
 		while (1)
 			;
 	}
-
-	init_pll(&ddr3b_333);
-	ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64);
-	ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
 }